An ASIC design of a high-speed Clock and Data Recovery circuit

Chi Wai Ng; Kai Hung Yu; Chiu Wing Sham; Chi Kong Tse

doi:10.4028/www.scientific.net/AMR.403-408.1218

An ASIC design of a high-speed Clock and Data Recovery circuit

Chi Wai Ng
, Kai Hung Yu
, Chiu Wing Sham
, Chi Kong Tse

The Hong Kong Polytechnic University

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

Abstract

Clock and Data Recovery (CDR) means that the digital data streams are sent without an accompanying clock signal. A digital CDR circuit is proposed as it does not depend on the special analog process and provide higher immunity to the noise. This design is fabricated using 0.13μm standard process and the circuit can support up to 5 GHz data rate to support the high speed standard. Compared to other CDR design with more advanced technology, our implementation can have similar performance but the manufacturing cost can be reduced.

Original language	English
Title of host publication	MEMS, NANO and Smart Systems
Pages	1218-1223
Number of pages	6
DOIs	https://doi.org/10.4028/www.scientific.net/AMR.403-408.1218
Publication status	Published - 1 Jan 2012
Event	2011 7th International Conference on MEMS, NANO and Smart Systems, ICMENS 2011 - Kuala Lumpur, Malaysia Duration: 4 Nov 2011 → 6 Nov 2011

Publication series

Name	Advanced Materials Research
Volume	403-408
ISSN (Print)	1022-6680

Conference

Conference	2011 7th International Conference on MEMS, NANO and Smart Systems, ICMENS 2011
Country/Territory	Malaysia
City	Kuala Lumpur
Period	4/11/11 → 6/11/11

Keywords

Clock and Data Recovery
Phase lock loop
Voltage control oscillator

ASJC Scopus subject areas

General Engineering

More information

10.4028/www.scientific.net/AMR.403-408.1218

Cite this

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title = "An ASIC design of a high-speed Clock and Data Recovery circuit",

abstract = "Clock and Data Recovery (CDR) means that the digital data streams are sent without an accompanying clock signal. A digital CDR circuit is proposed as it does not depend on the special analog process and provide higher immunity to the noise. This design is fabricated using 0.13μm standard process and the circuit can support up to 5 GHz data rate to support the high speed standard. Compared to other CDR design with more advanced technology, our implementation can have similar performance but the manufacturing cost can be reduced.",

keywords = "Clock and Data Recovery, Phase lock loop, Voltage control oscillator",

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AU - Tse, Chi Kong

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N2 - Clock and Data Recovery (CDR) means that the digital data streams are sent without an accompanying clock signal. A digital CDR circuit is proposed as it does not depend on the special analog process and provide higher immunity to the noise. This design is fabricated using 0.13μm standard process and the circuit can support up to 5 GHz data rate to support the high speed standard. Compared to other CDR design with more advanced technology, our implementation can have similar performance but the manufacturing cost can be reduced.

AB - Clock and Data Recovery (CDR) means that the digital data streams are sent without an accompanying clock signal. A digital CDR circuit is proposed as it does not depend on the special analog process and provide higher immunity to the noise. This design is fabricated using 0.13μm standard process and the circuit can support up to 5 GHz data rate to support the high speed standard. Compared to other CDR design with more advanced technology, our implementation can have similar performance but the manufacturing cost can be reduced.

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KW - Phase lock loop

KW - Voltage control oscillator

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ER -

An ASIC design of a high-speed Clock and Data Recovery circuit

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

More information

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