An ASIC design of a high-speed Clock and Data Recovery circuit

Chi Wai Ng, Kai Hung Yu, Chiu Wing Sham, Chi Kong Tse

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

Abstract

Clock and Data Recovery (CDR) means that the digital data streams are sent without an accompanying clock signal. A digital CDR circuit is proposed as it does not depend on the special analog process and provide higher immunity to the noise. This design is fabricated using 0.13μm standard process and the circuit can support up to 5 GHz data rate to support the high speed standard. Compared to other CDR design with more advanced technology, our implementation can have similar performance but the manufacturing cost can be reduced.
Original languageEnglish
Title of host publicationMEMS, NANO and Smart Systems
Pages1218-1223
Number of pages6
DOIs
Publication statusPublished - 1 Jan 2012
Event2011 7th International Conference on MEMS, NANO and Smart Systems, ICMENS 2011 - Kuala Lumpur, Malaysia
Duration: 4 Nov 20116 Nov 2011

Publication series

NameAdvanced Materials Research
Volume403-408
ISSN (Print)1022-6680

Conference

Conference2011 7th International Conference on MEMS, NANO and Smart Systems, ICMENS 2011
Country/TerritoryMalaysia
CityKuala Lumpur
Period4/11/116/11/11

Keywords

  • Clock and Data Recovery
  • Phase lock loop
  • Voltage control oscillator

ASJC Scopus subject areas

  • Engineering(all)

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