An air spacer technology for improving short-channel immunity of MOSFETs with raised source/drain and high-κ gate dielectric

Chunshan Yin; Philip Ching Ho Chan; Mansun Chan

doi:10.1109/LED.2005.846584

An air spacer technology for improving short-channel immunity of MOSFETs with raised source/drain and high-κ gate dielectric

Chunshan Yin, Philip Ching Ho Chan, Mansun Chan

Research output: Journal article publication › Journal article › Academic research › peer-review

19 Citations (Scopus)

Abstract

An air-spacer technology with raised source/drain (S/D) for ultrathin-body (UTB) silicon-on-insulator MOSFETs is developed. The results show that the poly raised S/D can effectively reduce the series resistance and the air spacer can effectively reduce the fringing capacitance. The air spacer is particularly useful when combined with high-K gate dielectric. The improved device characteristics are demonstrated experimentally and by extensive two-dimensional device simulation.

Original language	English
Pages (from-to)	323-325
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	26
Issue number	5
DOIs	https://doi.org/10.1109/LED.2005.846584
Publication status	Published - 1 May 2005
Externally published	Yes

Keywords

Air spacer
Gate insulator
High-κ dielectric
Raised source/drain (S/D)
Silicon-on-insulator (SOI)
Ultrathinbody (UTB)

ASJC Scopus subject areas

Electrical and Electronic Engineering

More information

10.1109/LED.2005.846584

Cite this

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abstract = "An air-spacer technology with raised source/drain (S/D) for ultrathin-body (UTB) silicon-on-insulator MOSFETs is developed. The results show that the poly raised S/D can effectively reduce the series resistance and the air spacer can effectively reduce the fringing capacitance. The air spacer is particularly useful when combined with high-K gate dielectric. The improved device characteristics are demonstrated experimentally and by extensive two-dimensional device simulation.",

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AU - Chan, Mansun

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AB - An air-spacer technology with raised source/drain (S/D) for ultrathin-body (UTB) silicon-on-insulator MOSFETs is developed. The results show that the poly raised S/D can effectively reduce the series resistance and the air spacer can effectively reduce the fringing capacitance. The air spacer is particularly useful when combined with high-K gate dielectric. The improved device characteristics are demonstrated experimentally and by extensive two-dimensional device simulation.

KW - Air spacer

KW - Gate insulator

KW - High-κ dielectric

KW - Raised source/drain (S/D)

KW - Silicon-on-insulator (SOI)

KW - Ultrathinbody (UTB)

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EP - 325

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 5

ER -

An air spacer technology for improving short-channel immunity of MOSFETs with raised source/drain and high-κ gate dielectric

Abstract

Keywords

ASJC Scopus subject areas

More information

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