Adaptive 2-D scheduling-based nonbinary majority-logic decoding for NAND flash memory

Cheng Wang, Jun Li, Jun Li, Lingjun Kong, Feng Shu, Francis C.M. Lau

Research output: Journal article publicationJournal articleAcademic researchpeer-review

1 Citation (Scopus)

Abstract

This brief presents a nonbinary adaptive 2D scheduling-based majority logic decoding (NB-ATS-MLGD) algorithm for NAND flash memory. The proposed algorithms provide considerable tradeoff between error-correcting capability and decoding complexity, and make the NB-MLGD decoding more attractive for practical purposes in the multi-level cells (MLC) NAND flash memory. The most significant feature of the proposed NB-ATS-MLGD algorithm is the 2D layered scheduling strategy, where the decoding orders of check nodes (CNs) and variable nodes (VNs) are both adaptive. By leveraging on the MLC flash memory bit error patterns, an early-correcting (EC) criterion is incorporated into the NB-ATS-MLGD algorithm. Furthermore, the simplification and parallelization of proposed algorithms make them more practical in NAND flash memory. Simulation results show that the proposed algorithms increase the lifetime of MLC flash memory up to 3000 program-and-erase (PE) cycles and have desirable convergence speed compared with the conventional non-binary MLGD algorithm. When at low PE cycles, the NB-EC-ATS-MLGD algorithm improves frame error rate (FER) performance by more than 3 order of magnitudes compared with the conventional non-binary MLGD algorithm.

Original languageEnglish
Article number8796433
Pages (from-to)1349-1353
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume67
Issue number7
DOIs
Publication statusPublished - Jul 2020

Keywords

  • 2D scheduling
  • majority-logic decoding (MLGD)
  • Multi-level cell (MLC)
  • NAND flash memory
  • non-binary low-density parity-check (NB-LDPC) codes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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