A two-level caching mechanism for demand-based page-level address mapping in NAND flash memory storage systems

Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

44 Citations (Scopus)

Abstract

The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping in the Flash Translation Layer (FTL) design. The demand-based approach can reduce the RAM footprint, but extra address translation overhead is also introduced which may degrade the system performance. This paper proposes a two-level caching mechanism to selectively cache the on-demand page-level address mappings by jointly exploiting the temporal locality and the spatial locality of workloads. The objective is to improve the cache hit ratio so as to shorten the system response time and reduce the block erase counts for NAND flash memory storage systems. By exploring the optimized temporal-spatial cache configurations, our technique can well capture the reference locality in workloads so that the hit ratio can be improved. Experimental results show that our technique can achieve a 31.51% improvement in hit ratio, which leads to a 31.11% reduction in average system response time and a 50.83% reduction in block erase counts compared with the previous work.
Original languageEnglish
Title of host publicationProceedings - 17th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2011
Pages157-166
Number of pages10
DOIs
Publication statusPublished - 1 Jun 2011
Event17th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2011 - Chicago, IL, United States
Duration: 11 Apr 201114 Apr 2011

Conference

Conference17th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2011
CountryUnited States
CityChicago, IL
Period11/04/1114/04/11

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

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