A three-dimensional stacked Fin-CMOS technology for high-density ULSI circuits

Xusheng Wu, Philip Ching Ho Chan, Shengdong Zhang, Chuguang Feng, Mansun Chan

Research output: Journal article publicationJournal articleAcademic researchpeer-review

21 Citations (Scopus)


In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized.
Original languageEnglish
Pages (from-to)1998-2003
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number9
Publication statusPublished - 1 Sept 2005
Externally publishedYes


  • FinFET
  • Silicon-on-insulator (SOI)
  • Three-dimensional integrated circuits (3-D IC)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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