A reliability enhanced address mapping strategy for three-dimensional (3-D) NAND flash memory

Yi Wang, Zili Shao, Chun Bun Henry Chan, Luis Angel D. Bathen, Nikil D. Dutt

Research output: Journal article publicationJournal articleAcademic researchpeer-review

29 Citations (Scopus)

Abstract

The linear scaling down of NAND flash memory is approaching its physical, electrical, and reliability limitations. To maintain the current trend of increasing bit density and reducing bit per cost, 3-D flash memory is emerging as a viable solution to fulfill the ever-increasing demands of storage capacity. In 3-D NAND flash memory, multiple layers are stacked to provide ultrahigh density storage devices. However, the physical architecture of 3-D flash memory leads to a higher probability of disturbance to adjacent physical pages and greatly increases bit error rates. This paper presents a novel physical-location-aware address mapping strategy for 3-D NAND flash memory. It permutes the physical mapping of pages and maximizes the distance between the consecutively logical pages, which can significantly reduce the disturbance to adjacent physical pages and effectively enhance the reliability. The proposed mapping strategy is applied to a representative flash storage system. Experimental results show that the proposed scheme can reduce uncorrectable page errors by 70.16% with less than 10.01% space overhead in comparison with the baseline scheme.
Original languageEnglish
Article number6678650
Pages (from-to)2402-2410
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number11
DOIs
Publication statusPublished - 1 Nov 2014

Keywords

  • 3-D integrated circuits
  • data storage systems
  • error correction codes
  • fault tolerance
  • flash memories
  • reliability

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this