A parallel-routing network for reliability inferences of single-parity-check decoder

Qing Lu, Zhuoer Shen, Chiu Wing Sham, Chung Ming Lau

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

Abstract

The computation of the reliability inferences among the variables of a single-parity-check (SPC) code is a common challenge to the implementation of channel decoders. Applicable to a variety of computational mechanisms using disparate kernels, a parallel-routing network has been developed, which is, compared to the state-of-art structure, exploring the best of its parallel nature for an improved timing performance. Furthermore, we assure that the proposed structure has no degradation in neither computation accuracy nor hardware complexity. With this structure, the LUT-based method becomes the optimal solution as a whole to implement an SPC decoder and other decoders containing it, like, for example, a low-density parity-check (LDPC) decoder. The improvement of the proposed design has been verified by a field-programmable gate array (FPGA), showing a 186% increase in clock rate for a 32-degree SPC decoder.
Original languageEnglish
Title of host publication2015 International Conference on Advanced Technologies for Communications, ATC 2015
PublisherIEEE Computer Society
Pages127-132
Number of pages6
Volume2016-January
ISBN (Electronic)9781467383745
DOIs
Publication statusPublished - 20 Jan 2016
Event8th International Conference on Advanced Technologies for Communications, ATC 2015 - Ho Chi Minh City, Viet Nam
Duration: 14 Oct 201516 Oct 2015

Conference

Conference8th International Conference on Advanced Technologies for Communications, ATC 2015
CountryViet Nam
CityHo Chi Minh City
Period14/10/1516/10/15

Keywords

  • Complexity theory
  • Decoding
  • Delays
  • Kernel
  • Reliability
  • Table lookup
  • Wires

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

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