A parallel-routing network for reliability inferences of single-parity-check decoder

The computation of the reliability inferences among the variables of a single-parity-check (SPC) code is a common challenge to the implementation of channel decoders. Applicable to a variety of computational mechanisms using disparate kernels, a parallel-routing network has been developed, which is, compared to the state-of-art structure, exploring the best of its parallel nature for an improved timing performance. Furthermore, we assure that the proposed structure has no degradation in neither computation accuracy nor hardware complexity. With this structure, the LUT-based method becomes the optimal solution as a whole to implement an SPC decoder and other decoders containing it, like, for example, a low-density parity-check (LDPC) decoder. The improvement of the proposed design has been verified by a field-programmable gate array (FPGA), showing a 186% increase in clock rate for a 32-degree SPC decoder.