TY - GEN
T1 - A novel switched-capacitor multilevel inverter offering modularity in design
AU - Fong, Y. C.
AU - Raman, S. Raghu
AU - Chen, M. Moonson
AU - Cheng, K. W.E.
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/4/18
Y1 - 2018/4/18
N2 - A new topology of switched-capacitor (SC) multilevel inverter (MLI) which enables modular design is presented in this paper. By employing the series-parallel SC technique, the proposed MLI provides voltage step-up capability and self-balancing of the capacitor voltage. Since the maximum voltage stress of the capacitors and the switches is limited by the proposed topology and independent of the number of output voltage levels, the SCMLI can be modularized with low-voltage SC units to form a scalable inverter with substantial decrease in production cost. In this paper, the key features and operation principle of the proposed topology are described. The capacitor voltage ripples and the associated energy loss of the SCMLI with staircase modulation under different loading conditions and operating frequencies are analyzed and the consideration for component sizing is discussed. The operation of the proposed topology is verified by the simulation and experiment on a 9-level SCMLI with three SC units.
AB - A new topology of switched-capacitor (SC) multilevel inverter (MLI) which enables modular design is presented in this paper. By employing the series-parallel SC technique, the proposed MLI provides voltage step-up capability and self-balancing of the capacitor voltage. Since the maximum voltage stress of the capacitors and the switches is limited by the proposed topology and independent of the number of output voltage levels, the SCMLI can be modularized with low-voltage SC units to form a scalable inverter with substantial decrease in production cost. In this paper, the key features and operation principle of the proposed topology are described. The capacitor voltage ripples and the associated energy loss of the SCMLI with staircase modulation under different loading conditions and operating frequencies are analyzed and the consideration for component sizing is discussed. The operation of the proposed topology is verified by the simulation and experiment on a 9-level SCMLI with three SC units.
KW - Multi-level inverter
KW - Series-parallel conversion
KW - Switched-capacitor circuit
UR - https://www.scopus.com/pages/publications/85046947755
U2 - 10.1109/APEC.2018.8341236
DO - 10.1109/APEC.2018.8341236
M3 - Conference article published in proceeding or book
AN - SCOPUS:85046947755
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 1635
EP - 1640
BT - APEC 2018 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2018
Y2 - 4 March 2018 through 8 March 2018
ER -