TY - GEN
T1 - A novel pipeline design for the realization of the prime factor FFT
AU - Lun, Daniel Pak Kong
AU - Siu, Wan Chi
PY - 1992/5/10
Y1 - 1992/5/10
N2 - In this paper, an extremely efficient pipeline architecture is proposed for the realization of the prime factor algorithm (PFA). By using the extended diagonal feature of the Chinese Remainder Theorem (CRT) mapping, we show that the data transactions during the computation can be efficiently carried out with the simplest control strategy. Due to this reason, the present approach has the least hardware requirement as compared to the previous propositions. Furthermore, in the case of multi-dimensional PFA computation, it does not require the computation to be split up into a number of two-dimensional ones. Consequently, the overhead which is required for data loading and data retrieval in each two-dimensional stage can be saved. In fact, all these savings are achieved by only using one more connection link which connects all the memory buffers via the extended diagonal of a multi-dimensional array.
AB - In this paper, an extremely efficient pipeline architecture is proposed for the realization of the prime factor algorithm (PFA). By using the extended diagonal feature of the Chinese Remainder Theorem (CRT) mapping, we show that the data transactions during the computation can be efficiently carried out with the simplest control strategy. Due to this reason, the present approach has the least hardware requirement as compared to the previous propositions. Furthermore, in the case of multi-dimensional PFA computation, it does not require the computation to be split up into a number of two-dimensional ones. Consequently, the overhead which is required for data loading and data retrieval in each two-dimensional stage can be saved. In fact, all these savings are achieved by only using one more connection link which connects all the memory buffers via the extended diagonal of a multi-dimensional array.
UR - http://www.scopus.com/inward/record.url?scp=54749129465&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.1992.229989
DO - 10.1109/ISCAS.1992.229989
M3 - Conference article published in proceeding or book
AN - SCOPUS:54749129465
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 160
EP - 163
BT - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Y2 - 10 May 1992 through 13 May 1992
ER -