A new formulation for the design of FIR filters with reduced hardware implementation complexity

Z. G. Feng, Ka Fai Cedric Yiu

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

Abstract

In this paper, we consider the design of finite-impulse response (FIR) filters, where the coefficients are expressed as sums of signed powers-of-two (SPT) terms. To consume less energy, the hardware implementation complexity is required to be reduced. That is, we need to minimize the number of SPT terms, subject to a given performance requirement This can be formulated as an integer programming problem and can be transformed into a simplified one with a conversion method, where the number of the variables is reduced. Then, an efficient algorithm based on discrete steepest descent algorithm is developed for solving this problem. For illustration, two numerical examples are solved.
Original languageEnglish
Title of host publication1st International Conference on Green Circuits and Systems, ICGCS 2010
Pages242-246
Number of pages5
DOIs
Publication statusPublished - 20 Sep 2010
Event1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai, China
Duration: 21 Jun 201023 Jun 2010

Conference

Conference1st International Conference on Green Circuits and Systems, ICGCS 2010
CountryChina
CityShanghai
Period21/06/1023/06/10

Keywords

  • FIR filters
  • SPT

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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