A methodology for converting polygon-based standards cells from bulk CMOS to SOI CMOS

Kevin Y. Wu, Philip Ching Ho Chan

Research output: Journal article publicationJournal articleAcademic researchpeer-review


A methodology has been developed to convert polygon-based full-custom bulk CMOS cells to SOI/CMOS. This methodology is implemented using the Cadence Design Systems Virtuoso environment. The methodology is demonstrated by converting the orbit scalable CMOSN standard cells. The results are quite good for small cells. However, for complex and highly optimized cell this methodology may lead to a slight increase in the cell area. This methodology can also be applied to further reduce the cell area if the SOI/CMOS cells are redesigned to take advantage of the low-power and high-performance capability of SOI/CMOS. This paper presents the detailed heuristics of the methodology.
Original languageEnglish
Pages (from-to)473-492
Number of pages20
JournalInternational Journal of Electronics
Issue number4
Publication statusPublished - 1 Jan 1997
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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