A methodology has been developed to convert polygon-based full-custom bulk CMOS cells to SOI/CMOS. This methodology is implemented using the Cadence Design Systems Virtuoso environment. The methodology is demonstrated by converting the orbit scalable CMOSN standard cells. The results are quite good for small cells. However, for complex and highly optimized cell this methodology may lead to a slight increase in the cell area. This methodology can also be applied to further reduce the cell area if the SOI/CMOS cells are redesigned to take advantage of the low-power and high-performance capability of SOI/CMOS. This paper presents the detailed heuristics of the methodology.
ASJC Scopus subject areas
- Electrical and Electronic Engineering