Abstract
The performance of a high-throughput long-distance communication system such as an optical transmission system is limited by the Net Coding Gain (NCG) of the Forward Error Correction (FEC) system. Summarizing the previous research works, Low-Density Parity-Check (LDPC) codes form one of the most promising FEC schemes to be applied in high-throughput communication systems. Designing a practical channel coding scheme with high code rate, low complexity, high throughput and extremely low error floor has always been a very challenging problem. Quasi-cyclic low-density parity-check (QC-LDPC) codes have been promising candidates to fulfill the above requirements but the implementation issues remain. In this paper, we propose a layered QC-LDPC decoder architecture with high code rate, low complexity, high throughput and excellent error performance. The architecture has been implemented using FPGA and the error performance has been shown to be good.
Original language | English |
---|---|
Title of host publication | 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 |
Pages | 475-478 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 1 Dec 2012 |
Event | 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, Taiwan Duration: 2 Dec 2012 → 5 Dec 2012 |
Conference
Conference | 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 |
---|---|
Country/Territory | Taiwan |
City | Kaohsiung |
Period | 2/12/12 → 5/12/12 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering