A layered QC-LDPC decoder architecture for high speed communication system

Chiu Wing Sham, Xu Chen, Wai M. Tam, Yue Zhao, Chung Ming Lau

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

13 Citations (Scopus)

Abstract

The performance of a high-throughput long-distance communication system such as an optical transmission system is limited by the Net Coding Gain (NCG) of the Forward Error Correction (FEC) system. Summarizing the previous research works, Low-Density Parity-Check (LDPC) codes form one of the most promising FEC schemes to be applied in high-throughput communication systems. Designing a practical channel coding scheme with high code rate, low complexity, high throughput and extremely low error floor has always been a very challenging problem. Quasi-cyclic low-density parity-check (QC-LDPC) codes have been promising candidates to fulfill the above requirements but the implementation issues remain. In this paper, we propose a layered QC-LDPC decoder architecture with high code rate, low complexity, high throughput and excellent error performance. The architecture has been implemented using FPGA and the error performance has been shown to be good.
Original languageEnglish
Title of host publication2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Pages475-478
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2012
Event2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, Taiwan
Duration: 2 Dec 20125 Dec 2012

Conference

Conference2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
CountryTaiwan
CityKaohsiung
Period2/12/125/12/12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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