A capped trimming hard-mask patterning technique for integration of nano-devices and conventional integrated circuits

Xusheng Wu; Philip Ching Ho Chan; Shengdong Zhang; Mansun Chan

doi:10.1109/EDSSC.2005.1635393

A capped trimming hard-mask patterning technique for integration of nano-devices and conventional integrated circuits

Xusheng Wu, Philip Ching Ho Chan, Shengdong Zhang, Mansun Chan

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

6 Citations (Scopus)

Abstract

Capped trimming hard-mask (CTHM) patterning technique has been developed based on standard materials and processing equipments. By using the CTHM technique, sub-50nm feature sized pattern can be realized based on 0.5μ m lithography technology. Imaging layer for capping and hard-mask layer shoul d have different etching selectivity and good contiguity to each other. Good control of trimming etching and hard-mask etching processes enable patterning of features with ultra-small dimension.

Original language	English
Title of host publication	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Pages	781-784
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2005.1635393
Publication status	Published - 1 Dec 2006
Externally published	Yes
Event	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC - Howloon, Hong Kong Duration: 19 Dec 2005 → 21 Dec 2005

Conference

Conference	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Country/Territory	Hong Kong
City	Howloon
Period	19/12/05 → 21/12/05

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

More information

10.1109/EDSSC.2005.1635393

Cite this

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title = "A capped trimming hard-mask patterning technique for integration of nano-devices and conventional integrated circuits",

abstract = "Capped trimming hard-mask (CTHM) patterning technique has been developed based on standard materials and processing equipments. By using the CTHM technique, sub-50nm feature sized pattern can be realized based on 0.5μ m lithography technology. Imaging layer for capping and hard-mask layer shoul d have different etching selectivity and good contiguity to each other. Good control of trimming etching and hard-mask etching processes enable patterning of features with ultra-small dimension.",

author = "Xusheng Wu and Chan, {Philip Ching Ho} and Shengdong Zhang and Mansun Chan",

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doi = "10.1109/EDSSC.2005.1635393",

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pages = "781--784",

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Wu, X, Chan, PCH, Zhang, S & Chan, M 2006, A capped trimming hard-mask patterning technique for integration of nano-devices and conventional integrated circuits. in 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC., 1635393, pp. 781-784, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Howloon, Hong Kong, 19/12/05. https://doi.org/10.1109/EDSSC.2005.1635393

A capped trimming hard-mask patterning technique for integration of nano-devices and conventional integrated circuits. / Wu, Xusheng; Chan, Philip Ching Ho; Zhang, Shengdong et al.
2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. 2006. p. 781-784 1635393.

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

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A capped trimming hard-mask patterning technique for integration of nano-devices and conventional integrated circuits

Abstract

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ASJC Scopus subject areas

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