A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes

Qing Lu, Jianfeng Fan, Chiu Wing Sham, Wai M. Tam, Chung Ming Lau

Research output: Journal article publicationJournal articleAcademic researchpeer-review

30 Citations (Scopus)


In this paper, we propose a new class of quasi-cyclic low-density parity-check (QC-LDPC) codes, namely cyclically-coupled QC-LDPC (CC-QC-LDPC) codes, and their RAM-based decoder architecture. CC-QC-LDPC codes have a simple structure and are constructed by cyclically-coupling a number of QC-LDPC subcodes. They can achieve throughput and error performance as excellent as LDPC convolutional codes, but with much lower hardware requirements. They are therefore promising candidates for future generations of communication systems such as long-haul optical communication systems. In particular, a rate-5/6 CC-QC-LDPC decoder has been implemented onto a field-programmable gate array (FPGA) and it achieves a throughput of 3.0 Gb/s at 100 MHz clock rate with 10-iteration decoding. No error floor is observed up to an Eb/N0of 3.50 dB, where all 1.14× 1016transmitted bits have been decoded correctly.
Original languageEnglish
Article number7370816
Pages (from-to)134-145
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number1
Publication statusPublished - 1 Jan 2016


  • Cyclically-coupled QC-LDPC code
  • decoder architecture
  • FPGA implementation
  • QC-LDPC code

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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