3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and beyond

Do Won Kim; Hong Yu Li; Ka Fai Chang; Woon Leng Loh; Ser Choong Chong; Hong Cai; Bhattacharya Surya

doi:10.1109/ECTC.2018.00129

3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and beyond

Do Won Kim, Hong Yu Li, Ka Fai Chang, Woon Leng Loh, Ser Choong Chong, Hong Cai, Bhattacharya Surya

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

12 Citations (Scopus)

Abstract

In this study, 3D electronic-photonic integrated circuits (EPIC) packaging using through silicon vias (TSV) has been demonstrated. Silicon photonic integrated circuit (Si-PIC) in SOI which has TSV for electrical interconnection is flip-chip bonded on a Si interposer using electrochemical plating (ECP) bumps of 90 μm-diameter in this 3D EPIC packaging. A 750 ?-cm of high-resistivity SOI and silicon wafers are used for PIC chip with TSV and interposer respectively. Measured insertion loss (S21) for the 3D EPIC packaged test vehicle using TSV is less than 3.5dB and return loss (S11) is less than -13dB up to 50 GHz. This high-bandwidth 3D EPIC packaging platform can be applied for the system-on-packaging (SOP) modules and subsystems such as optical transceiver (TRx) and radio-over-fiber (ROF) solutions.

Original language	English
Title of host publication	Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	834-840
Number of pages	7
ISBN (Print)	9781538649985
DOIs	https://doi.org/10.1109/ECTC.2018.00129
Publication status	Published - 7 Aug 2018
Externally published	Yes
Event	68th IEEE Electronic Components and Technology Conference, ECTC 2018 - San Diego, United States Duration: 29 May 2018 → 1 Jun 2018

Publication series

Name	Proceedings - Electronic Components and Technology Conference
Volume	2018-May
ISSN (Print)	0569-5503

Conference

Conference	68th IEEE Electronic Components and Technology Conference, ECTC 2018
Country/Territory	United States
City	San Diego
Period	29/05/18 → 1/06/18

Keywords

3D system-onn-package
50Gps/ch data transmission
Data center
Electronic-photonic integrated circuits (EPIC)
Optical interconnections
Optical transceiver
Through silicon vias (TSVs)

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

More information

10.1109/ECTC.2018.00129

Cite this

Kim, D. W., Li, H. Y., Chang, K. F., Loh, W. L., Chong, S. C., Cai, H., & Surya, B. (2018). 3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and beyond. In Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018 (pp. 834-840). Article 8429642 (Proceedings - Electronic Components and Technology Conference; Vol. 2018-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECTC.2018.00129

Kim, Do Won ; Li, Hong Yu ; Chang, Ka Fai et al. / 3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and beyond. Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 834-840 (Proceedings - Electronic Components and Technology Conference).

@inproceedings{829dd0d7e02f49b4b1a341965f0b626c,

title = "3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and beyond",

abstract = "In this study, 3D electronic-photonic integrated circuits (EPIC) packaging using through silicon vias (TSV) has been demonstrated. Silicon photonic integrated circuit (Si-PIC) in SOI which has TSV for electrical interconnection is flip-chip bonded on a Si interposer using electrochemical plating (ECP) bumps of 90 μm-diameter in this 3D EPIC packaging. A 750 ?-cm of high-resistivity SOI and silicon wafers are used for PIC chip with TSV and interposer respectively. Measured insertion loss (S21) for the 3D EPIC packaged test vehicle using TSV is less than 3.5dB and return loss (S11) is less than -13dB up to 50 GHz. This high-bandwidth 3D EPIC packaging platform can be applied for the system-on-packaging (SOP) modules and subsystems such as optical transceiver (TRx) and radio-over-fiber (ROF) solutions.",

keywords = "3D system-onn-package, 50Gps/ch data transmission, Data center, Electronic-photonic integrated circuits (EPIC), Optical interconnections, Optical transceiver, Through silicon vias (TSVs)",

author = "Kim, {Do Won} and Li, {Hong Yu} and Chang, {Ka Fai} and Loh, {Woon Leng} and Chong, {Ser Choong} and Hong Cai and Bhattacharya Surya",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 68th IEEE Electronic Components and Technology Conference, ECTC 2018 ; Conference date: 29-05-2018 Through 01-06-2018",

year = "2018",

month = aug,

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doi = "10.1109/ECTC.2018.00129",

language = "English",

isbn = "9781538649985",

series = "Proceedings - Electronic Components and Technology Conference",

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Kim, DW, Li, HY, Chang, KF, Loh, WL, Chong, SC, Cai, H & Surya, B 2018, 3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and beyond. in Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018., 8429642, Proceedings - Electronic Components and Technology Conference, vol. 2018-May, Institute of Electrical and Electronics Engineers Inc., pp. 834-840, 68th IEEE Electronic Components and Technology Conference, ECTC 2018, San Diego, United States, 29/05/18. https://doi.org/10.1109/ECTC.2018.00129

3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and beyond. / Kim, Do Won; Li, Hong Yu; Chang, Ka Fai et al.
Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 834-840 8429642 (Proceedings - Electronic Components and Technology Conference; Vol. 2018-May).

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

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AU - Kim, Do Won

AU - Li, Hong Yu

AU - Chang, Ka Fai

AU - Loh, Woon Leng

AU - Chong, Ser Choong

AU - Cai, Hong

AU - Surya, Bhattacharya

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AB - In this study, 3D electronic-photonic integrated circuits (EPIC) packaging using through silicon vias (TSV) has been demonstrated. Silicon photonic integrated circuit (Si-PIC) in SOI which has TSV for electrical interconnection is flip-chip bonded on a Si interposer using electrochemical plating (ECP) bumps of 90 μm-diameter in this 3D EPIC packaging. A 750 ?-cm of high-resistivity SOI and silicon wafers are used for PIC chip with TSV and interposer respectively. Measured insertion loss (S21) for the 3D EPIC packaged test vehicle using TSV is less than 3.5dB and return loss (S11) is less than -13dB up to 50 GHz. This high-bandwidth 3D EPIC packaging platform can be applied for the system-on-packaging (SOP) modules and subsystems such as optical transceiver (TRx) and radio-over-fiber (ROF) solutions.

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T3 - Proceedings - Electronic Components and Technology Conference

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PB - Institute of Electrical and Electronics Engineers Inc.

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Kim DW, Li HY, Chang KF, Loh WL, Chong SC, Cai H et al. 3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and beyond. In Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 834-840. 8429642. (Proceedings - Electronic Components and Technology Conference). doi: 10.1109/ECTC.2018.00129

3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and beyond

Abstract

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Conference

Keywords

ASJC Scopus subject areas

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