3D integrated circuit using large grain polysilicon film

V. W.C. Chan, Philip Ching Ho Chan, Mansun Chan

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

2 Citations (Scopus)

Abstract

3-D CMOS IC technology built on two layers of large grain polysilicon is presented. These stacked layers are vertically interconnected allowing shorter interconnect to improve the logic speed. The large grain polysilicon-on-insulator (LPSOI) film is formed by the recrystallization of amorphous silicon through Metal Induced Lateral Crystallization (MILC). The crystallization region obtained can cover multiple transistors and the grain size is much larger than the transistor size. An oxide layer separates two layers of devices and forms an interlayer dielectric. The electrical performance of the LPSOI devices is presented. Inverters, ring-oscillators and shift registers further confirm that the recrystallized techniques forming the 3-D structures are feasible.
Original languageEnglish
Title of host publication2001 6th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2001 - Proceedings
PublisherIEEE
Pages58-61
Number of pages4
Volume1
ISBN (Electronic)0780365208, 9780780365209
DOIs
Publication statusPublished - 1 Jan 2001
Externally publishedYes
Event6th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2001 - Shanghai, China
Duration: 22 Oct 200125 Oct 2001

Conference

Conference6th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2001
Country/TerritoryChina
CityShanghai
Period22/10/0125/10/01

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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