3-Dimensional integration for interconnect reduction in for nano-CMOS technologies

Mansun Chan, Shengdong Zhang, Xinnan Lin, Xusheng Wu, Philip Ching Ho Chan

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review


This paper describes a method to integrate nonplanar multi-gate CMOS devices in the third dimension. The technology is based on highly scalable multi-gate MOSFET structures which are promising for nano-scale integration. The extension to have active devices placed the third dimension allow significant reduction in the interconnect loading. We have demonstrated the potential of such technology though experimentally fabricated devices as well as detail system level analysis.
Original languageEnglish
Title of host publication2006 IEEE Region 10 Conference, TENCON 2006
Publication statusPublished - 9 Aug 2007
Externally publishedYes
Event2006 IEEE Region 10 Conference, TENCON 2006 - Hong Kong, Hong Kong
Duration: 14 Nov 200617 Nov 2006


Conference2006 IEEE Region 10 Conference, TENCON 2006
Country/TerritoryHong Kong
CityHong Kong

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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