3-Dimensional integration for interconnect reduction in for nano-CMOS technologies

Mansun Chan; Shengdong Zhang; Xinnan Lin; Xusheng Wu; Philip Ching Ho Chan

doi:10.1109/TENCON.2006.343731

3-Dimensional integration for interconnect reduction in for nano-CMOS technologies

Mansun Chan, Shengdong Zhang, Xinnan Lin, Xusheng Wu, Philip Ching Ho Chan

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

Abstract

This paper describes a method to integrate nonplanar multi-gate CMOS devices in the third dimension. The technology is based on highly scalable multi-gate MOSFET structures which are promising for nano-scale integration. The extension to have active devices placed the third dimension allow significant reduction in the interconnect loading. We have demonstrated the potential of such technology though experimentally fabricated devices as well as detail system level analysis.

Original language	English
Title of host publication	2006 IEEE Region 10 Conference, TENCON 2006
DOIs	https://doi.org/10.1109/TENCON.2006.343731
Publication status	Published - 9 Aug 2007
Externally published	Yes
Event	2006 IEEE Region 10 Conference, TENCON 2006 - Hong Kong, Hong Kong Duration: 14 Nov 2006 → 17 Nov 2006

Conference

Conference	2006 IEEE Region 10 Conference, TENCON 2006
Country/Territory	Hong Kong
City	Hong Kong
Period	14/11/06 → 17/11/06

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

More information

10.1109/TENCON.2006.343731

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title = "3-Dimensional integration for interconnect reduction in for nano-CMOS technologies",

abstract = "This paper describes a method to integrate nonplanar multi-gate CMOS devices in the third dimension. The technology is based on highly scalable multi-gate MOSFET structures which are promising for nano-scale integration. The extension to have active devices placed the third dimension allow significant reduction in the interconnect loading. We have demonstrated the potential of such technology though experimentally fabricated devices as well as detail system level analysis.",

author = "Mansun Chan and Shengdong Zhang and Xinnan Lin and Xusheng Wu and Chan, {Philip Ching Ho}",

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AU - Lin, Xinnan

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AB - This paper describes a method to integrate nonplanar multi-gate CMOS devices in the third dimension. The technology is based on highly scalable multi-gate MOSFET structures which are promising for nano-scale integration. The extension to have active devices placed the third dimension allow significant reduction in the interconnect loading. We have demonstrated the potential of such technology though experimentally fabricated devices as well as detail system level analysis.

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DO - 10.1109/TENCON.2006.343731

M3 - Conference article published in proceeding or book

SN - 1424405491

SN - 9781424405497

BT - 2006 IEEE Region 10 Conference, TENCON 2006

T2 - 2006 IEEE Region 10 Conference, TENCON 2006

Y2 - 14 November 2006 through 17 November 2006

ER -

3-Dimensional integration for interconnect reduction in for nano-CMOS technologies

Abstract

Conference

ASJC Scopus subject areas

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